The present invention relates generally to a method and apparatus for providing signal conversion, and more particularly to a parallel processing method and apparatus for converting signals between digital and analog.
The performance of analog and digital converters is typically quantified by two primary parameters, speed (in samples per second) and resolution (in bits). Designers of analog and digital converters typically face the challenge of trading off the resolution of a converter with its speed.
One type of prior art, high-speed analog-to-digital converter, is implemented using M time-interleaved, moderate speed, analog-to-digital converters (ADCs) configured in an array. In a typical time-interleaved converter, the M ADCs comprising the converter are triggered successively at a rate equal to 1/M times the effective sample rate of the overall converter. One drawback of time-interleaved converters is limited speed and resolution due to the sensitivity of these converters to mismatches between characteristics (including gain, phase and DC offset) of the M ADCs and due to clock timing errors.
A block diagram of a second type of prior art converter 10 is shown in FIG. 1. The converter 10 includes M analysis filters 12A-12D, M synthesis filters 14A-14D, M ADCs 16A-16D, M downsamplers 18A-18D, M upsamplers 20A-20D and an adder 22. The analysis filters 12A-12D partition a wideband input signal, u[n], into M narrow subband signals, which are downsampled by a factor M in the downsamplers 16A-16D. Each of the ADCs 16A-16D converts one of the subband signals from analog to digital. The upsamplers 20A-20D increase the sampling rate of the signals by a factor equal to M. The synthesis filters 14A-14D in combination with the adder 22 reconstruct the input signal in digital format. The frequency response for typical filters used as the analysis filters 12A-12D in the converter 10 are shown in FIG. 2.
One advantage of the converter 10 over the typical time-interleaved converters discussed above is an improvement in speed and resolution that can be achieved due to an attenuation in the effects of gain and phase mismatches between ADCs in the array of ADCs. In one prior art converter, disclosed in U.S. Pat. No. 5,392,044 to Kotzin et al., that utilizes the architecture shown in FIG. 1, a fully discrete-time quadrature mirror filter (QMF) (e.g., utilizing switched-capacitors) is used to implement the analysis filters 12A-12D. One drawback of this design is that the use of switched-capacitors limits the speed of the system and introduces switching noise which can limit the signal-to-noise ratio of the system. In addition, this converter is only capable of converting between discrete-time analog and discrete-time digital signals.
U.S. Pat. No. 5,568,142 to Velazquez et al., discloses a converter, having the architecture shown in FIG. 1, that overcomes some of the drawbacks of the converter disclosed by Kotzin et al. The converter disclosed by Velazquez et al. uses continuous-time analog analysis filters to feed each ADC in the converter and discrete-time digital synthesis filters to reconstruct the digitized signal. The primary drawbacks of this approach are that it uses high-order continuous-time analog filters with high stopband attenuation. Further, the converter disclosed in U.S. Pat. No. 5,568,142 is only capable of converting between continuous-time analog signals and discrete-time digital signals.
In addition to being concerned with the speed and resolution provided when selecting a converter architecture, designers of analog and digital converters are also typically concerned with the ease and accuracy of generating (or designing) and calibrating an analog and digital converter for a selected converter architecture. The ease and accuracy by which a specific analog and digital converter can be generated and calibrated is highly dependent on the architecture selected.
The discrete-time filter bank converter disclosed by Kotzin can be generated using standard digital filter bank generation techniques. However, disadvantages of these techniques are that round-off errors in implementing analog electronics in the converter can limit the resolution of the system, and the analog filters cannot typically be built with the same level of accuracy and precision of the digital filters, thereby limiting the performance of the system.
The converter disclosed by Velazquez et al. in U.S. Pat. No. 5,568,142 can be generated, as described in the patent, using an iterative optimization of the continuous-time filters followed by an iterative optimization of the discrete-time filters. The primary disadvantage of this approach is that it can be computationally intensive and is not guaranteed to converge to an accurate result.
Many prior art converters and other electronic systems are calibrated for peak performance by injecting a known test signal, measuring performance, and adjusting the electronics to correct for errors. Wideband pseudorandom signals have been used as calibration signal sources for electronic systems. The primary disadvantage of this calibration technique is that it can mask the magnitude and sources of individual errors and make it difficult to isolate and correct the individual errors.
The converter disclosed by Velazquez et al. in U.S. Pat. No. 5,568,142 can be calibrated, as described in the patent, by measuring the performance of subband signals followed by an iterative optimization of the digital filters to compensate for any errors detected. The primary disadvantages of this technique are that it is hardware intensive (since it requires measurement of each of the M subband signals), computationally complex and not guaranteed to converge to an accurate result.
It is desirable to provide an analog and digital converter that overcomes the drawbacks of the prior art discussed above.
Embodiments of the present invention are directed to methods and apparatus for providing analog and digital conversion that overcome drawbacks of the prior art discussed above. It should be noted that the term xe2x80x9canalog and digital converterxe2x80x9d as used herein includes analog-to-digital converters and digital-to-analog converters.
In one general aspect, the invention features a converter for converting an input signal from a first format to a second format. The converter includes a decomposition section, a converter array operatively coupled to the decomposition section, and a recombination section operatively coupled to the converter array. The decomposition section includes an input to receive the input signal, a splitter to divide the input signal into a plurality of signals, a plurality of signal outputs, each of which provides as an output one of the plurality of signals, and a clock circuit having a plurality of clock outputs for providing sample clocks to the converter array. The converter array includes a plurality of converters, each of the converters having a signal input to receive one of the plurality of signals, a clock input to receive one of the sample clocks and an output that provides a converted signal. At least one of the decomposition section and the recombination section includes filters for filtering either the plurality of signals or the plurality of converted signals.
The first format of the converter system can be analog, the second format can be digital, each of the converters of the converter array can be an analog to digital converter, and the recombination section can include a plurality of filters for filtering each of the converted signals. The clock circuit can be constructed and arranged to introduce a phase delay in at least one of the sample clocks The decomposition section can be constructed and arranged to receive as the input signal at least one of a continuous-time analog signal and a discrete-time analog signal. The recombination section can include a plurality of outputs that provide a plurality of converter output signals, each of the converter output signals being of the second format and corresponding to one of the plurality of output signals of the decomposition section. The recombination section can include an adder for combining a plurality of signals to create a converter output signal, wherein the converter output signal is of the second format and is representative of the input signal. The decomposition section can include a sampler that receives the input signal and provides an output sampled signal. The sampler can be constructed and arranged to operate on intermediate frequency data of the input signal. The recombination section can include a compensation section that corrects errors introduced into the converted signals by the converters in the converter array, and the compensation section can be adapted to correct errors introduced by the decomposition section. In the converter, the first format can be digital, the second format can be analog, each of the converters of the converter array can be a digital to analog converter, the decomposition section can include a plurality of filters for filtering each of the plurality of signals, and the recombination section can include a plurality of filters for filtering each of the converted signals.
In another general aspect, the invention features a method for generating a converter system that converts signals from a first format to a second format. The method can include steps of selecting converters for the converter system that convert signals from the first format to the second format, determining a value of residual mismatch error in the signals converted, and selecting filters for the converter system, having stopband attenuation characteristics based on the value of residual mismatch error. In the method, the filters can be selected such that the stopband attenuation of the filters is proportional to the value of residual mismatch error.
In another general aspect, the present invention features a method for generating a converter system that converts signals from a first format to a second format, wherein one of the formats is a continuous-time format. The method includes steps of selecting converters for the converter system that convert signals from the first format to the second format, and selecting continuous-time filters for the conversion system based on a transformation of discrete-time filters such that frequency responses of the continuous-time filters approximate that of the discrete-time filters. In the method, the transformation can be based on a ratio of polynomials.
In yet another general aspect, the present invention features a method of calibrating a system having an input to receive an input signal and an output that provides an output signal. The method includes steps of injecting a comb signal having selected frequency components into the input of the system, measuring performance of the system, and altering characteristics of the system based on the performance measured. The selected frequency components can be selected based on frequencies of predicted error signals of the system, such that the selected frequency components do not coincide with the frequencies of the predicted error signals.
The step of injecting can include a step of generating the comb signal such that the phase of each of the selected frequency components is not coherent with the phase of other selected frequency components. The system can be a converter system for converting a signal from a first format to a second format. The step of measuring performance can include a step of evaluating an output signal at the signal output of the system. The system can include a plurality of converters that generate a plurality of converted signals, and the step of measuring performance can include a step of evaluating the plurality of converted signals.
In another general aspect, the present invention features a method for converting an input signal from a first format to a second format. The method includes steps of receiving the input signal, splitting the input signal into a plurality of signals, generating a plurality of clock signals each having a clock period, converting the plurality of signals from the first format to the second format using a sampling rate determined by the clock period of the plurality of clock signals to produce a plurality of converted signals, and filtering either the plurality of signals or the plurality of converted signals or both.
In the method, the first format can be analog, the second format can be digital, and the step of converting can include a step of converting the plurality of signals from analog to digital. The method can further include a step of introducing a phase delay in at least one of the sample clock signals, such that the at least one of the sample clock signals has a phase that is delayed with respect to that of at least one other of the sample clock signals. The step of receiving can include a step of receiving at least one of a continuous-time analog signal and a discrete-time analog signal. The method can further include a step of combining the plurality of converted signals to create a converter output signal, wherein the converter output signal is of the second format and is representative of the input signal. The method can further include a step of sampling the input signal. The step of sampling can include a step of operating on intermediate frequency data of the input signal. The method can further include a step of correcting errors introduced into the converted signals during the step of converting. The step of correcting can include a step of correcting for errors introduced during the step of splitting. In the method, the first format can be digital, the second format can be analog, and the step of converting can include a step of converting the plurality of signals from digital to analog.
In another general aspect, the present invention features a method for generating a converter system that converts an input signal from a first format to a second format, the converter system including an analog processing section, a digital processing section, a clock skew circuit for providing a plurality of clock signals, and a plurality of converters to receive the plurality of clock signals and operatively coupled between the analog processing section and the digital processing section. The method for generating includes steps of selecting the converters, generating the analog processing section, setting a time skew between each of the plurality of clock signals, and selecting a frequency response of the digital processing section to provide an accurate representation of the input signal, wherein the step of setting a time skew includes determining the time skew such that the frequency response of the digital processing section for providing an accurate representation of the input signal is conjugate symmetric.
In another general aspect, the present invention features a method for generating a discrete-time analog processing section of a converter system. The method includes steps of utilizing a lossless factorization technique to generate multi-stage filters for use in the discrete-time analog processing section, and providing gain normalization factors between stages of the filters.
In still another general aspect, the present invention features a method for generating a converter system having a designated frequency range that converts an input signal from a first format to a second format, the converter system including an analog processing section, a digital processing section and a plurality of converters operatively coupled between the analog processing section and the digital processing section. The method for generating includes steps of selecting the converters, generating the analog processing section, and selecting a frequency response of the digital processing section such that aliasing errors are cancelled over the designated frequency range of the device.
The converter system generated by the method has a phase response, and the step of selecting a frequency response can include a step of setting the phase response of the converter system to be a linear phase response.
In another general aspect, the present invention features a method for generating a converter system that converts an input signal from a first format to a second format. The converter system includes an analog processing section, a digital processing section and a plurality of converters operatively coupled between the analog processing section and the digital processing section. The method includes steps of selecting the converters, generating the analog processing section, setting the delay of the converter system, and selecting a frequency response of the digital processing section to provide an accurate representation of the input signal. The step of setting the system delay includes determining the system delay such that the frequency response of the digital processing section for providing an accurate representation of the input signal is conjugate symmetric.